Democratizing Microelectronics: IEEE Division I Open Silicon Initiative

By, Fernando Guarin Ph.D., Director, Division I, 2026-2027

In a global technology landscape driven by semiconductors, the barriers to custom integrated circuit (IC) design and fabrication have historically remained steep. High software licensing fees, proprietary Process Design Kits (PDKs), and prohibitive manufacturing costs have long restricted chip fabrication to commercial giants and elite research institutions.

Stepping forward to disrupt this paradigm is the IEEE Division I Open Silicon Initiative. Managed cross-functionally by representatives from the five Division I organizations—the IEEE Solid-State Circuits Society (SSCS), IEEE Circuits and Systems Society (CASS), IEEE Electron Devices Society (EDS), IEEE Council on Electronic Design Automation (CEDA), and the IEEE Nanotechnology Council (NTC)—the initiative has set a bold mission: to provide open access, standardized tools, and global mentoring to students and researchers eager to learn physical chip design.

Rather than focusing solely on theoretical coursework, the framework centers on real-world applications, bridging the gap between hardware description language and physical silicon. The architectural blueprint of this open hardware ecosystem relies on four tightly integrated operational pillars:

1. Microelectronic Bootcamps: Using accessible platforms like Tiny Tapeout, the initiative provides hands-on tapeout experience for beginners. By reducing costs and complexity, thousands of participants can design, verify, and physically manufacture their projects.
2. The Chipathon: Aimed at expanding advanced engineering capabilities, this annual competition guides global teams through specialized design paths—ranging from foundational analog/digital blocks and sensor circuits to agentic, AI/LLM-assisted EDA tool flows.
3. UNIC-CAS and University Curriculum Integration: Tailored for higher education, a dedicated Q3 2026 framework allows professors to integrate open PDKs and open-source tools directly into engineering syllabi. Students design chips during the semester, submit them for fabrication, and test the physical hardware in a follow-up lab course the next term.
4. Academic Validation Tracks: To ensure long-term visibility, the initiative is formalizing a publication pathway where finalists present their designs and artifact disclosures at specialized open-source circuits workshops and conference tracks.

The appetite for open-source semiconductor design has surpassed initial expectations, achieving explosive global traction in 2026. As of late April, the program had 1,875 active participants, guided by 212 project leaders worldwide. Interest spans multiple regions, with a substantial concentration in India, alongside robust workshop footprints in the United States, Mexico, Colombia, Brazil, Malaysia, Bangladesh, and Japan. By the May 2026 deadlines, the ecosystem yielded 53 active workshops in 27 countries, resulting in 1,686 verified participants submitting 200 distinct designs and 221 chip tiles ready for production.

By standardizing open-source Electronic Design Automation (EDA) flows and absorbing financial risk through institutional funding, the IEEE Division I Open Silicon Initiative is shifting semiconductor education from an exclusive discipline into a shared, collaborative ecosystem. As physical development boards ship to global participants later this year, the dream of making custom silicon design accessible to anyone, anywhere, is officially becoming a reality. The goal is to extend beyond Division I to all IEEE Operating Units with a need and desire to fabricate chips.